RISC-V (pronounced risc-five) is a brand-new instruction set architecture (ISA) that’s open to customize and free to use by anyone. The ISA is only a few years old, but both large and small companies, such as Nvidia, Western Digital, and Esperanto, are now planning to use RISC-V chips to power their products.
Why RISC-V Was Created
The initial version of the RISC-V ISA started development at the University of California, Berkeley, in 2010. The academics there wanted to develop a more modern and more efficient ISA for the 21st century that removes the legacy cruft and many mistakes built into multi-decade old instruction sets such as x86 and ARM. The researchers also wanted an ISA that is fully open and free for anyone to use for any purpose without having to pay any royalties to anyone.
In 2014, version 2.0 of the ISA was released, and that’s when many of the big players in the technology industry started becoming interested in it. If 1.0 was more of a research curiosity, 2.0 showed that the ISA could actually be used in production by large players who wanted to save money on royalties or simply wanted a much larger degree of freedom when designing their own CPUs.
In 2015, the RISC-V Foundation was created with more than 100 members and a board of directors that included companies such as Google, Nvidia, Western Digital, NXP, Microsemi, and Bluespec, as well as a representative from UC Berkeley. Since then, chip companies such as AMD, Qualcomm, and IBM have also joined the members list.
The foundation released version 2.2 of the RISC-V ISA specification earlier this year. Mozilla also recently announced that the memory safe Rust programming language, which the organization is now using to rewrite core components of the Firefox browser, supports the RISC-V ISA as a compilation target.
Western Digital Commits To Shipping “Billions” Of RiSC-V Cores
At the a recent RISC-V Workshop event, Western Digital, one of the largest manufacturers of storage devices, announced that it’s going to lead the industry in the switch to the more open RISC-V ISA by committing to ship over one billion RISC-V cores per year in its devices.
WD said that the purpose for implementing more powerful RISC-V cores into its products is that this will bring computation closer to data. The movement of the data will be minimized, which should bring increased performance and efficiency to its customers.
WD hopes that after switching all of its product lineups to using RISC-V microcontrollers, it will be able to ship over two billion RISC-V cores across its product categories.
Esperanto Promises “AI At The Edge” With RISC-V Cores
Esperanto Technologies a chip designer from Mountain View, California, also announced at the latest workshop that it will start developing energy-efficient AI chips using the RISC-V ISA.
“Esperanto’s goal is to make RISC-V the architecture of choice for the most demanding AI and machine learning applications which will drive computing innovation for the next decade,” said Esperanto CEO Dave Ditzel.
“RISC-V is so simple and extensible that we can deliver world class TeraFlop levels of computing without needing to resort to proprietary instruction sets, thereby greatly increasing software availability,” he noted.
He also added that the company will build a 16-core “ET-Maxion” 64-bit chip, which will have single-thread performance, as well as a 4,096-core “ET-Minion” energy-efficient chip, with each core having its own floating point unit.
Dave Ditzel has a long history of supporting RISC instruction sets. He was founder of Transmeta, a company that tried to build RISC chips that could emulate x86 programs on them, and he worked on the SPARC architecture at Sun Microsystems. Ditzel also worked at Intel for six years, working on various high-performance chip projects.
Western Digital CTO Martin Fink also announced at the RISC-V workshop that they’ve made a strategic investment in Esperanto in order to help build the RISC-V ecosystem.
Nvidia Quietly Adopting RISC-V, Too
Last year, Nvidia quietly revealed that it’s going to build its next-generation GPU microcontroller on the RISC-V ISA. The new RISC-V microcontroller is expected to improve performance by more than three times compared to its existing Falcon microcontroller. The RISC-V microcontroller will also include some significant security features that the current microcontroller is lacking, which could be of use in the autonomous driving industry, for instance.
We’re not going to see RISC-V take the market by storm and compete with Intel and ARM in high-end smartphones, PCs, and servers for at least a few more years. However, RISC-V’s modern ISA, which brings high efficiency, better security, as well as the openness of the architecture combined with the royalty-free license, may prove irresistible to many companies.